1. Field
This disclosure relates to a system and method for real time cognitive processing for data fusion in a dynamic environment. More particularly, the present disclosure describes a method and system for real-time, adaptive, intelligent, low power, high productive and miniaturized processing using custom VLSI design for target detection and classification.
2. Description of Related Art
A general purposed computer can typically simulate or support just about any application through iterated computation in a sequential manner. Such general purpose computers typically use an architecture known as a Von Neumann architecture that consists of input/output, memory, and an Arithmetic Logic Unit. The Von Neumann architecture (or Von Neumann machine) is a sequential computation architecture. One draw back of the Von Neumann architecture is that it is slow, regardless of computer speed.
To deal with complex data fusion applications as required in military applications, particularly remote, real time applications related to the dynamic environment, the Von Neumann machine may not be effective for demands such as compactness, real time processing, adaptive system and low power. There are many types of data (e.g., IR, LIDAR, RADAR, Visual, Olfactory) that need to be processed and fused in real time. In data processing and fusion, especially for sensors, time can be critical to every millisecond. The speed requirements may present a challenge for a digital computer and the architecture of a system as a whole. For example, sensors may collect analog data that will be converted to a digital format before sending the data to the digital machine in a sequential manner for algorithmic computation. Each sequential step requires a delay and processing time to digest data, and finally, the solution that is provided by the computer may no longer be valid.
In contrast, a neural network architecture is a parallel processing technique and its performance can be much faster as compared with the digital machines. See, for example, J. J. Hopfield, “Neural networks and physical systems with emergent collective computational abilities,” Proc. Natl. Acad. Sci. USA, vol. 79, pp. 2554-2558, 1982 and T. A. Duong, S. P. Eberhardt, T. Daud, and A. Thakoor, “Learning in neural networks: VLSI implementation strategies,” Fuzzy logic and Neural Network Handbook, Chap. 27, Ed: C. H. Chen, McGraw-Hill, 1996. However, neural network hardware is typically not as fully-programmable as a digital computer. In neural network, one computer (or set of computers) may perform the learning and download a weight set to a neural network chip (see for example, E. Fiesler, T. Duong, and A. Trunov, “Design of neural network-based microchip for color segmentation,” SPIE Proceeding of Applications and Science of Computational Intelligence part III, Vol. 4055, pp. 228-237, Florida, May 2000, and T. X. Brown, M. D. Tran, T. A. Duong, T. Daud, and A. P. Thakoor, Cascaded VLSI neural network chips: Hardware learning for pattern recognition and classification, Simulation, 58, 340-347, 1992), while another computer (or set of computers) can perform on-chip learning with limited programming capability (i.e., not flexible for other applications) (see, for example, T. A. Duong, T. Daud, “On-Chip Learning of Hyper-Spectra Data for Real-Time Target Recognition”, Proceeding of IASTED Intelligent System and Control, pp. 305-308, Honolulu, Hi., August 14-17, 2000; B. Girau, “On-Chip learning of FPGA-Inspired neural nets,” Proceeding of International of Neural Networks IJCNN'2001, Vol. 1, pp. 212-215, 2001; C. Lu, B. Shi, and L. Chen, “A Programmable on-chip learning neural network with enhance characteristics,” The 2001 IEEE Inter. Symposium Circuit and Systems ISCAS 2001, Vol. 2, pp. 573-576, 2001; and G. M. Bo, D. D. Caviglia, and M. Valle, “An on-chip learning neural network,” Proc. Inter. Neural Networks IJCNN'2000, Vol. 4, pp. 66-71, 2000). A neural network hardware implementation also has a two-fold problem: reliable learning techniques in limited weight space for learning network convergence in a parallel architecture (see, for example, T. A. Duong and Allen R. Stubberud, “Convergence Analysis Of Cascade Error Projection—An Efficient Learning Algorithm For Hardware Implementation,” International Journal of Neural System, Vol. 10, No. 3, pp. 199-210, June 2000; Hoehfeld, M. and Fahlman, S., “Learning with limited numerical precision using the cascade-correlation algorithm,” IEEE Trans. Neural Networks, vol. 3, No. 4, pp. 602-611, 1992; and P. W. Hollis, J. S. Harper, and J. J. Paulos, “The Effects of Precision Constraints in a Backpropagation learning Network,” Neural Computation, vol. 2, pp. 363-373, 1990), and a flexible architecture to solve a wide range of problems. To break these problems, one must devise a reliable learning neural network technique that is able to learn under a limited weight space in milliseconds and a novel architecture that is fully programmable through instruction sets, from which the real time adaptive network in a chip can be achieved to solve a real time applications in a dynamic environment.
Hence, there is a need in the art for a fully programmable processing architecture that can address complex data fusion applications in a dynamic environment.